CCD image sensors typically include an array of photosensitive areas (or “pixels”) that collect charge carriers in response to illumination. The collected charge is subsequently transferred from the array of pixels and converted to a voltage from which an image may be reconstructed by associated circuitry. FIG. 1 depicts a conventional CCD image sensor 100 that contains an array of pixels 110 (each of which may include or consist essentially of a photodiode) arranged in columns. A vertical CCD (VCCD) 120 is disposed next to each column of pixels 110, and the VCCDs 120 are connected to a horizontal HCCD (HCCD) 130. Following an exposure period, charge is transferred from the pixels 110 into the VCCDs 120, which subsequently shift the charge, row-by-row in parallel, into the HCCD. The HCCD then transfers the pixel charge serially to output circuitry that includes a floating diffusion sense node 140 and an output buffer amplifier 150. The charge from the HCCD is converted, pixel-by-pixel, into voltage at the sense node 140 and amplifier 150, and the signal is then transferred to additional circuitry (either on-chip or off-chip) for reconstruction into an image.
Systems such as digital cameras utilizing CCD image sensors typically need to operate at high frame rates for, e.g., machine vision applications and video display. For cameras using conventional CCD image sensors, these high frame rates can result in high power consumption to generate so many horizontal scanning CCD clocking voltages and currents. Much of the power is generally lost to heat, which degrades the operation of the camera through higher imager dark current. Other potential disadvantages include increased readout noise due to the high signal-sampling frequency utilized during the readout operation.
One technique that has been utilized to address the power-consumption and noise issues with CCD image sensors is the separation of the pixel array and the readout circuitry onto separate chips, which are then bonded together. For example, FIG. 2 depicts an image-sensor system 200 consisting of an imaging array chip 210 and a readout chip 220. As described above with respect to FIG. 1, fabricated on chip 210 are columns of pixels 230 (individual pixels are not depicted for convenience) each adjoined by a VCCD 240. A readout circuit 250 is fabricated on the discrete chip 220, and chips 210, 220 are electrically and physically connected in hybrid fashion via multiple ball bonds 260. However, hybrid systems such as system 200 are expensive and involve complicated fabrication steps, as typically the chips 210, 220 are each fabricated with different semiconductor fabrication processes. Moreover, these hybrid systems are often less reliable than single-chip solutions due to the chip-to-chip interconnections. Thus, there is a need for monolithic CCD image sensors having reduced power consumption, low noise, and high reliability.